1015 2011-04-28 14:13:35 +0000 Crownbay BSP does not have SMT activated. 2011-05-20 07:23:46 +0000 1 1 7 Build System, Metadata & Runtime BSPs bsps-configuration 1.0 Other x86 RESOLVED FIXED Medium normal 1.1 1 marc.ferland tom.zanussi dvhart sgw yp.bsp.watcher yp.watcher --- --- --- oldest_to_newest 13474 0 marc.ferland 2011-04-28 14:13:35 +0000 The e660 supports 2 active threads a.k.a. HyperThreading (see: http://ark.intel.com/Product.aspx?id=52495) but the kernel configuration for this board does not seem to activate it. This results in the system seeing only one "CPU". 13526 1 dvhart 2011-05-02 14:54:53 +0000 I suggest a fix along the lines of that done for the n450, but in the meta/cfg/kernel-cache/bsp scc file. You can use the new cfg/smp.scc fragment. 13543 2 marc.ferland 2011-05-03 07:45:00 +0000 (In reply to comment #1) > I suggest a fix along the lines of that done for the n450, but in the > meta/cfg/kernel-cache/bsp scc file. You can use the new cfg/smp.scc fragment. Do you know if the EMGD binary driver needs to be rebuilt in order to work on an SMP enabled system? I've tried enabling SMP on a test platform (with the kernel in laverne), everything seemed fine until it tried to load the binary kernel module which failed with "Invalid module format". P.S. I would have attached the log files, but I do not have access to the platform anymore, sorry!... 13545 3 dvhart 2011-05-03 08:00:11 +0000 I wouldn't have thought so, but I'm not sure. Tom any thoughts? 13546 4 tom.zanussi 2011-05-03 08:05:15 +0000 (In reply to comment #3) > I wouldn't have thought so, but I'm not sure. Tom any thoughts? The 'invalid module format' would suggest only a kernel mismatch, so yeah, looks like the module didn't get rebuilt to match the kernel. The userspace stuff should be fine as is with SMP or not, anyway it's binary which we can't recompile in any case. 13606 5 dvhart 2011-05-05 20:42:56 +0000 Marc, would you like to take a stab and submitting fixes for these? You mentioned no longer having access, if that is a permanent situation, we can work on pushing it through (just might be a bit longer). 13608 6 tom.zanussi 2011-05-05 23:25:09 +0000 (In reply to comment #5) > Marc, would you like to take a stab and submitting fixes for these? You > mentioned no longer having access, if that is a permanent situation, we can > work on pushing it through (just might be a bit longer). I can test it if you want to submit a patch but don't have the hardware, or I can submit a tested patch, etc, either way is fine with me... 13617 7 marc.ferland 2011-05-06 10:53:42 +0000 (In reply to comment #6) > (In reply to comment #5) > > Marc, would you like to take a stab and submitting fixes for these? You > > mentioned no longer having access, if that is a permanent situation, we can > > work on pushing it through (just might be a bit longer). > > I can test it if you want to submit a patch but don't have the hardware, or I > can submit a tested patch, etc, either way is fine with me... Darren, Tom, I have again access to the platform, I will test a fix in the linux/wrs/cfg/kernel-cache/bsp/crownbay/crownbay.cfg file on my laverne build and I'll also try the new wrs/cfg/kernel-cache/cfg/smp.scc Darren was talking about. 13647 8 145 marc.ferland 2011-05-09 14:58:37 +0000 Created attachment 145 Patch for SMP support on crownbay. 13648 9 marc.ferland 2011-05-09 15:00:06 +0000 Tom, Darren, Here's a small patch against master I've made to add SMP support to crownbay. Things compile fine and the .config file contains SMP stuff. I wasn't able to test it on a live platform though because of bug #986. 13649 10 tom.zanussi 2011-05-09 15:55:42 +0000 (In reply to comment #9) > Tom, Darren, > > Here's a small patch against master I've made to add SMP support to crownbay. > Things compile fine and the .config file contains SMP stuff. > > I wasn't able to test it on a live platform though because of bug #986. Hmm, I'm going to have the same problem testing this - looks like we need to figure out 986. 13869 11 161 tom.zanussi 2011-05-18 08:40:14 +0000 Created attachment 161 updated version of 145: Patch for SMP support on crownbay. same as 145: Patch for SMP support on crownbay, but with srcrev part removed and a reject fixed 13871 12 tom.zanussi 2011-05-18 08:45:06 +0000 Finally was able to test this patch on new hardware, works fine. Attached is a new version of the patch - essentially the same, but I updated the SRCREVs independently already so that doesn't have to be part of the patch. Also fixed a small reject, the bbappend must have changed since then. Anyway, if you want to submit the patch with those changes, I can pull it into master and then when I get the chance will migrate it over into the meta branch of the kernel repo. before: root@crownbay-noemgd:~# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 38 model name : Genuine Intel(R) CPU @ 1.30GHz stepping : 1 cpu MHz : 1299.874 cache size : 512 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov\ pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_per\ f mon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr p\ d cm movbe lahf_lm dts tpr_shadow vnmi bogomips : 2599.74 clflush size : 64 cache_alignment : 64 address sizes : 32 bits physical, 48 bits virtual power management: after: root@crownbay-noemgd:~# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 38 model name : Genuine Intel(R) CPU @ 1.30GHz stepping : 1 cpu MHz : 1300.175 cache size : 512 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 1 apicid : 0 initial apicid : 0 fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov\ pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_per\ f mon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr p\ d cm movbe lahf_lm dts tpr_shadow vnmi bogomips : 2600.35 clflush size : 64 cache_alignment : 64 address sizes : 32 bits physical, 48 bits virtual power management: processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 38 model name : Genuine Intel(R) CPU @ 1.30GHz stepping : 1 cpu MHz : 1300.175 cache size : 512 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 1 apicid : 1 initial apicid : 1 fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov\ pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_per\ f mon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr p\ d cm movbe lahf_lm dts tpr_shadow vnmi bogomips : 2600.16 clflush size : 64 cache_alignment : 64 address sizes : 32 bits physical, 48 bits virtual power management: 13899 13 marc.ferland 2011-05-19 07:04:15 +0000 (In reply to comment #12) > Finally was able to test this patch on new hardware, works fine. Attached is a > new version of the patch - essentially the same, but I updated the SRCREVs > independently already so that doesn't have to be part of the patch. Also fixed > a small reject, the bbappend must have changed since then. > > Anyway, if you want to submit the patch with those changes, I can pull it into > master and then when I get the chance will migrate it over into the meta branch > of the kernel repo. > Tom, Should I send my patch to the mailing list or attach it to the bug report? I see many people are sending patches on the mailing list, is this the preferred way? 13900 14 tom.zanussi 2011-05-19 07:43:28 +0000 (In reply to comment #13) > (In reply to comment #12) > > Finally was able to test this patch on new hardware, works fine. Attached is a > > new version of the patch - essentially the same, but I updated the SRCREVs > > independently already so that doesn't have to be part of the patch. Also fixed > > a small reject, the bbappend must have changed since then. > > > > Anyway, if you want to submit the patch with those changes, I can pull it into > > master and then when I get the chance will migrate it over into the meta branch > > of the kernel repo. > > > Tom, > Should I send my patch to the mailing list or attach it to the bug report? I > see many people are sending patches on the mailing list, is this the preferred > way? Yeah, sending it to the list is preferred (yocto@yoctoproject.org). Thanks! 13931 15 tom.zanussi 2011-05-20 07:23:46 +0000 Fixed by meta-intel commit 54a572b1d4d4bfd018fc969cc2a4e1c3ba66bb39. 145 2011-05-09 14:58:37 +0000 2011-05-09 14:58:37 +0000 Patch for SMP support on crownbay. 0001-Add-SMP-support-to-crownbay.patch text/plain 2816 marc.ferland RnJvbSA2MmRkZWFmZGMwZjk4MThmNGViNjA4YTMwMWY2NDgxYzIyMjI3NWY3IE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiBNYXJjIEZlcmxhbmQgPGZlcmxhbmRtQHNvbmF0ZXN0LmNvbT4K RGF0ZTogU2F0LCA3IE1heSAyMDExIDE5OjQ3OjQ4IC0wNDAwClN1YmplY3Q6IFtQQVRDSF0gQWRk IFNNUCBzdXBwb3J0IHRvIGNyb3duYmF5LgoKLS0tCiBtZXRhLWNyb3duYmF5L2NvbmYvbWFjaGlu ZS9jcm93bmJheS1ub2VtZ2QuY29uZiAgICB8ICAgIDIgKy0KIG1ldGEtY3Jvd25iYXkvY29uZi9t YWNoaW5lL2Nyb3duYmF5LmNvbmYgICAgICAgICAgIHwgICAgMiArLQogLi4uL2xpbnV4L2xpbnV4 LXlvY3RvLXN0YWJsZV9naXQuYmJhcHBlbmQgICAgICAgICAgfCAgICAyICsrCiAuLi4vcmVjaXBl cy1rZXJuZWwvbGludXgvbGludXgteW9jdG9fZ2l0LmJiYXBwZW5kICB8ICAgIDEgKwogNCBmaWxl cyBjaGFuZ2VkLCA1IGluc2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEv 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