Bug 6727

Summary: Feature request: provide an option to configure any of the HDR26 GPIO_S5[2:0] pins for wake
Product: [Hardware Platforms] MinnowBoard MAX Firmware Reporter: Ivan Rouzanov <ivan.rouzanov>
Component: minnowmax-edk2Assignee: David Anders <david.anders>
Status: RESOLVED MOVED QA Contact:
Severity: enhancement    
Priority: Medium CC: austin.zhang, danders, david.wei, dvhart, mike.wu, shifeix.a.lu, sjolley.yp.pm, warthog9, xing.wei, yoctoproject
Version: 2C A1   
Target Milestone: Production Release   
Hardware: MinnowBoard Max   
OS: Multiple   
Whiteboard:
OS type for building Yocto: --- Type of Regression: ---
Verified: Documentation change: Don't know
Attachments:
Description Flags
Engineering drop for GPIO_S5_0
none
Item"GPIO Wake Capability" for GPIO_S5_0 none

Description Ivan Rouzanov 2014-09-16 02:20:43 UTC
Currently there is no option to generate external wake signal to the MinnowBoard MAX to wake it up externally from S3.
The feature request is for Firmware to provide an option to configure (probable one is enough) of GPIO_S5[2:0] for GPIO F6 to generate SCI wake so device can be woken up externally.
Comment 1 Darren Hart 2014-09-16 03:40:05 UTC
We should allow for any and all of the available wake pins to be configured as such - individually.
Comment 2 David_Wei 2014-09-28 07:45:52 UTC
I do not think native function F6 is what you want. (1) F6 is a native fuction which is connected to WAKE# signal of PCIe devices, which is routed to ACPI's PCIe GPE, rather than GPIO GPE. I think we still need to use GPIO F0. (2) And SUS0 does not have F6 function.
Comment 3 Darren Hart 2014-09-29 16:29:08 UTC
David, that sounds correct to me.
Comment 4 David_Wei 2014-09-30 14:37:09 UTC
Firmware team update:
After (1)enabling edge detection and wake capability of GPIO_SUSx, (2)routing GPIO_SUSx to GPE GPIO_SUSx and (3)enabling wake capability of GPE GPIO_SUSx, GPIO_SUS0 (GPIO_S5[0]) could wake the system from S3 and S5. But the same code implementation cannot make GPIO_SUS1 and GPIO_SUS2 get the wake capability. Our team is debugging this isse.
Comment 5 John 'Warthog9' Hawley 2014-10-30 23:15:13 UTC
This is a question, that since the pins go through a level shifter, is this even possible, or is this going to be a "known issue" that isn't really resolvable with the current board?
Comment 6 Darren Hart 2014-11-20 23:30:55 UTC
David Wei:

Please enable a menu to "Enable GPIO Wake" for each of GPIO_S5[2:0] to GPIO GPE (F0 I think you said).

From Linux, we enter the sleep states as follows (most distributions have GUIs for this, but the following always works):

S1:
# echo "standby" > /sys/power/standby

S3:
# echo "mem" > /sys/power/state

S4:
# echo "disk" > /sys/power/state

S5: (from wikipedia)
G2 (S5), Soft Off: G2/S5 is almost the same as G3 Mechanical Off, except that the power supply unit (PSU) still supplies power, at a minimum, to the power button to allow return to S0. A full reboot is required. No previous content is retained. Other components may remain powered so the computer can "wake" on input from the keyboard, clock, modem, LAN, or USB device.

I don't know how to enter S5 or how this differs from G3 (mechanical off).

Ivan, can you provide instructions for entering these states from Windows?
Comment 7 Ivan Rouzanov 2014-11-20 23:41:18 UTC
On Windows:

To find out supported S-states, launch CMD.EXE as Administrator and run:
POWERCFG -A

If S3 is not supported, make sure Intel Graphics is installed.
To enable S4 run POWERCFG -H ON

For S3:
Press Windows key + I, Click on Power and then Sleep

For S4:
launch CMD.EXE as Administrator and run:
SHUTDOWN.EXE /H

For S5:
launch CMD.EXE as Administrator and run:
SHUTDOWN.EXE /S /T 0
Comment 8 Ivan Rouzanov 2014-11-21 00:26:55 UTC
S5 is what we need, not G3 (G3 is board not powered - cannot wake from that).
Comment 9 David_Wei 2014-11-21 00:38:54 UTC
We will first provide an engineering drop which gets all required registers programmed for GPIO_S5_0, so that CircuitCo can start to verify it as soon as possible. Meanwhile, we will add a setup option to enable/disbale this feature feature.
Comment 10 Lu_Shifei 2014-11-21 02:19:18 UTC
Created attachment 2254 [details]
Engineering drop for GPIO_S5_0

David Anders:
Can you test this Engineering drop for GPIO_S5_0 on your side? See attachment:"MNW2MAX1.X64.0074.R03.1411210910.zip". Thanks!
Comment 11 Stephen K Jolley 2014-11-24 21:00:01 UTC
Information given, out of NEEDINFO
Comment 12 Lu_Shifei 2014-12-05 02:14:46 UTC
Created attachment 2284 [details]
Item"GPIO Wake Capability" for GPIO_S5_0

Currently, we add setup item "GPIO Wake Capability", which can enable/disable
GPIO_S5_0 for S3,by following setup option:Device Manager->System Setup->South Cluster Configuration->Miscellaneous Configuration->GPIO Wake Capability.
Test image,see "Item"GPIO Wake Capability" for GPIO_S5_0".
Comment 13 wei xing 2014-12-11 05:48:12 UTC
hi shifei,
I used the firmware in attachment 2284 [details] and enable the gpio wake up option,
but kernel gpio driver didn't work any more. So if I enable it, gpio will be selected to IO access instead of memory access right?
Comment 14 Lu_Shifei 2014-12-11 08:17:58 UTC
Weixing,
Yes,GPIO wake up is accessed by I/O access only.Which type OS included kernel gpio driver didn't work any more on your side?
Comment 15 wei xing 2014-12-22 09:49:58 UTC
Hi all,
I think the problem for gpio is the mmio and io register can't co-exist which means if i enable io access,
the mmio register was invalid and can't be read/write anymore.These two register set both have some functions
that the other one dont have, like io register can enable wake up function, but mmio didn't have.
You can configure the gpio pullup, pulldown or non pull state by acessing mmio register, but io register can't...
I really don't know why the gpio controller register was designed like this, fix me if I am wrong.
Comment 16 David_Wei 2014-12-24 09:17:29 UTC
According to Intel public datasheet for Intel Atom processor E3800, When a GPIO is selected via the IO USE_SEL, Memory accesses are denied (pconf0, 
pconf1 and pad_val).  

Maybe you could try following bits to switch between IO and MMIO mode.


Register: 
Sus Use Select 1 (cfio_ioreg_SUS_USE_SEL_31_0_)—Offset 0h
Access via PCU Proxy, the register is setting the correspanding GPIO to be selected and to be changed to IO access instead of the default Memory access. Bit 0 will set 
GPIO[0], and bit 1 will set GPIO[1] and so on.
Comment 17 wei xing 2014-12-25 06:04:24 UTC
hi david,
The big problem is if I select io access, not only mmio access was denied, but also the configuration function provided by the mmio access register was invalid, seems like the mmio access register all reset to default value.
Comment 18 Michael Halstead 2015-01-12 21:37:31 UTC
Updating assignee to new office e-mail address.
Comment 19 austin.zhang 2015-01-14 10:01:18 UTC
Hi all,

What we want to achieve is:
Considering from power-saving POV, we will try our best to put the minnow-max system into S3 once possible, after then, we will wake up the system to S0 if there would be something needed to do. So we are connecting one movement detection sensor to minnow-max by GPIO as wakeup source, and once the sensor found movement (like human's activities), the system will back to S0.

Now as Xing had mentioned before, if we use I/O way to set the wake-up capability of GPIO, we 'can' wakeup the system from S3 by GPIO "BUT" due to under that situation, the default value of GPIO is high, and we have no way to config high/low as MMIO way doesn't work now, and also have no way to pull it low enough by this sensor, so we always failed to wake up the system by GPIO.
Under this situation, the only way to wake-up system is connecting Pin to GND so the signal is low enough and can be identified by HW then wakeup the system.

We are trying to connect one resistance in this board so that by that same sensor, we also can get one 'low enough' value to GPIO pin.

But it is one ugly workaround obviously even be successful.

So, for our minnow-max, that means we DON'T have one decent way to wake up the system from S3 by GPIO?

P.S, we also try to wake up the system from S3 by w-o-wireless, but also failed. See bug#7109.
https://bugzilla.yoctoproject.org/show_bug.cgi?id=7109 

Any suggestions would be appreciated!
Comment 20 austin.zhang 2015-01-14 10:10:45 UTC
(In reply to comment #19)
one correction

- We are trying to connect one resistance in this board 
+ We are trying to connect one resistance to this sensor
Comment 21 Stephen K Jolley 2017-06-13 18:04:38 UTC
We are no longer tracking in Yocto Project Bugzilla MinnowBoard and MinnowBoard-MAX HW and firmware bugs.